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A compact functional verification flow for a RISC-V 321 based core

The structure of a functional verification flow used for the design of a RISC-V core is presented. The paper offers a guide on the test-planning used and details of the flow architecture, showing how to integrate the Universal Verification Methodology with the required, reference models, while imple...

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Main Author: Molina Robles, Roberto (author)
Other Authors: Solera Bolanos, Edgar (author), García Ramírez, Ronny (author), Chacón Rodríguez, Alfonso (author), Rimolo Donadio, Renato (author), Arnaud Maceira, Alfredo (author)
Format: article
Language:English
Published: 2020
Subjects:
Functional verification
RISC-V 321
UVM
System Verilog
EDA tools
Architecture
Test generation
Compiler
Processor
Simulation
Coverage
Regression
Reference model
Online Access:https://hdl.handle.net/10895/1549
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Summary:The structure of a functional verification flow used for the design of a RISC-V core is presented. The paper offers a guide on the test-planning used and details of the flow architecture, showing how to integrate the Universal Verification Methodology with the required, reference models, while implementing key futures in standard verification environments, such as testing regressions and code and structural coverage. The designed flow is compact yet efficient, making it affordable for small design teams, without requiring extra investment other than the already necessary licenses for RTL synthesis and the eventual fabrication of the chip.

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