CMOS level shifters from 0 to 18 V output
A design methodology for level shifters voltage translators, where the output voltage ranges from 0 to 18 V, and the input voltage ranges from 2 to 5.5 V in a 0.6 lm CMOS-HV technology, is presented. This family of circuits have a special interest in the case of implantable medical devices where is...
Збережено в:
| Автор: | |
|---|---|
| Інші автори: | , |
| Формат: | article |
| Мова: | Англійська |
| Опубліковано: |
2021
|
| Предмети: | |
| Онлайн доступ: | https://hdl.handle.net/10895/1553 |
| Теги: |
Немає тегів, Будьте першим, хто поставить тег для цього запису!
|
| Резюме: | A design methodology for level shifters voltage translators, where the output voltage ranges from 0 to 18 V, and the input voltage ranges from 2 to 5.5 V in a 0.6 lm CMOS-HV technology, is presented. This family of circuits have a special interest in the case of implantable medical devices where is common to handle previously unknown voltages either positive or negative, above or below the control logic supply VDD. Two application examples are presented: a composite switch to control negative stimuli voltage pulses, and a multi-channel programmable charge-pump voltage multiplier, aimed at charging the output capacitors of an IMD. |
|---|