The design methodology of a sample and hold for a low-power sensor interface circuit
I tiakina i:
| Kaituhi matua: | |
|---|---|
| Ētahi atu kaituhi: | |
| Hōputu: | article |
| Reo: | Pāniora |
| I whakaputaina: |
1997
|
| Ngā marau: | |
| Urunga tuihono: | https://hdl.handle.net/20.500.12008/20728 |
| Ngā Tūtohu: |
Kāore He Tūtohu, Me noho koe te mea tuatahi ki te tūtohu i tēnei pūkete!
|
Ngā tūemi rite: The design methodology of a sample and hold for a low-power sensor interface circuit
- Power-aware design methodologies for embedded wireless sensors and microsystems
- Design of a micropower signal conditioning circuit for a piezoresistive acceleration sensor
- Techniques for ultra low power integrated temperature sensors
- Fully-Depleted SOI CMOS Technology for Low-Voltage Low-Power Mixed Digital/Analog/Microwave Circuits
- Ultra-low power temperature sensor
- Potential of SOI for low-power design. (Digital and Analog)